This invention relates generally to amplifier circuitry and, more specifically, to class D amplifier circuitry having a modulator and a switching power stage.
Class D amplifiers are well known and widely used. Class D amplifiers are particularly useful in applications where high efficiency is required, such as in power amplifiers, regulators and similar types of circuitry. The high efficiency of the class D amplifier (e.g., about 90%) makes it particularly attractive for use in battery-powered applications, such as portable radios, tape and CD players, and personal communicators, including wireless devices such as cellular telephones and mobile terminals.
A disadvantage of the class D amplifier is that it generates noise due to the on-off switching of the active element(s) in the switching stage.
Reference is made to FIG. 1 for showing a conventional audio reproduction path (ARP) 1. The ARP 1 includes a digital-to-analog converter (DAC) 2 that receives an N-bit digital code representing the digitized audio signal to be reproduced. The analog output signal of the DAC 2 is fed to a lowpass smoothing filter 3, and the smoothed analog signal is then input to a linear audio power amplifier 4 (e.g., class A, B, AB). The output of the linear power amplifier 4 drives an external speaker 5. Single bit sigma-delta techniques ( a digital modulator and single bit DAC) to achieve the desired conversion accuracy are typically employed by the DAC 2.
While the digital modulator can be implemented with state-of-the-art integrated circuit fabrication techniques, such as digital CMOS techniques using narrow linewidths and low supply voltages, implementing the DAC stage and linear power amplifier 4 have become increasingly difficult to implement using these processes, while achieving a desired performance level. As such, a mixed-signal process can be used.
While high performance can be achieved with the linear amplifier 4, such as a class A, B or AB amplifier, the power efficiency is below 50% at best, resulting in the generation of excess heat as well as increased battery power consumption.
FIG. 2 shows a conventional class D ARP 6. An input N-bit digital signal (e.g., 13 to 16 bits) is a applied to a digital modulator 7 where it is modulated to a one bit pulse width modulated (PWM) or a pulse density modulated (PDM) format. The PWM or PDM signal drives a switching driver 8, such as a conventional H-bridge driver configuration or an inverter, that provides a buffered modulated digital signal to a low pass filter 9. The resulting filtered analog signal is used to drive the external speaker 5.
A significant advantage of the class-D amplifier chain depicted in FIG. 2 is the high efficiency that can be achieved, typically as much as 90%. However, the linearity is degraded by the presence of second order effects, such as noise coupling from the power supply lines and non-ideal H-bridge switching characteristics. This is shown in FIGS. 3A and 3B, where the difference between the ideal and the actual PWM signal corresponds to driver errors, power supply noise and power supply variations. The switching and quantization noise spectrum also contains high noise levels at high frequencies, resulting in the need for the external lowpass (LC) filter 9 to avoid unnecessary power transmission and consumption, as well as to reduce undesirable noise radiation (EMC).
An analog implementation of the modulator 7 for class D operation is possible to achieve. This approach avoids many of the non-ideal characteristics introduced by the use of the digital modulator. However, a DAC is required to interface between the analog and the digital domains, reducing the overall compactness and increasing the cost and power consumption.
It should be noted that the use of the digital modulator 7 actually provides a number of advantages for mobile wireless terminals. These advantages include an increased integration level (for achieving a so-called xe2x80x9csingle-chipxe2x80x9d baseband subsystem), ease of design and testing, and compactness due to the inherent digital to analog conversion. However, a direct class D implementation (no feedback) can only achieve about 50-60 dB SNDR, as it is limited by the non-ideal switching characteristics. Also, the tolerance for power supply noise (power supply rejection ratio PSRR) is also low, typically about 0-6 dB.
One known approach to solving these problems is to employ the use of feedback based on a high resolution analog-to-digital converter (ADC) to measure the output signal waveform for deriving a correction signal. However, the required resolution and speed of the ADC makes this approach unattractive for applications where cost is an important consideration.
Another feedback technique can be found in WO98/44626, where digital modulation is used with analog pulse width correction. The pulse width correction is based on a reference PWM waveform and analog pulse width adjustment. However, the use of analog components and circuits is generally a disadvantage when it is desired to implement the circuitry in a low power consumption digital integrated circuit (e.g., in a digital CMOS IC).
It is a first object and advantage of this invention to provide a class D amplifier circuit arrangement that employs feedback from the output to the digital input of the power stage, using a minimum of passive or active analog components.
It is a further object and advantage of this invention to provide a class D amplifier circuit arrangement that employs a feedback loop implemented with a comparator, providing a one bit converter function indicating a sign of a loop error signal, that has an output that may be digitally filtered and employed to digitally adjust a power stage input signal to attenuate noise resulting from power supply noise and variations and power stage non-linearities.
The foregoing and other problems are overcome and the foregoing objects and advantages are realized by methods and apparatus in accordance with embodiments of this invention.
Disclosed is a method and circuitry for compensating a pulse width modulated (PWM) signal. The method includes steps of generating a PWM signal for application to a driver stage; obtaining a filtered difference between the PWM signal and a version of the same PWM signal after the driver stage; generating a correction signal that is indicative of a sign of the filtered difference; and using the correction signal for adjusting at least one of the leading edge or the trailing edge of the PWM signal so as to compensate the version of the same PWM signal after the driver stage. The steps of obtaining and generating include steps of RC filtering, digital comparison and digital filtering. In the preferred embodiment the step of generating generates a one-bit correction signal. The correction signal is used to compensate the version of the same PWM signal after the driver stage for driver stage non-linearities and for power supply noise and variations.
The step of adjusting includes initial steps of combining two successive digital samples into one longer PWM sample, and interpolating the longer PWM sample by a factor in a range of about two to eight. The step of adjusting can also operate on one digital sample, where the one sample is simply doubled before interpolation. The PWM sample is preferably in a thermometer format, although other formats can be employed.
In the presently preferred embodiment the step of generating generates the PWM signal from a multi-bit signal output from a sigma-delta modulator, where the multi-bit signal has 2n quantization levels, where n is in a range of about two to about eight.